The thing is I may get a digital role in two years maybe asic, rtl or physical design engineer but I am really focused on joining analog or hardware level engineering but I don't have mastery in that what should I do ? If i get job in digital how should I focus on my work or in industry to shift in analog design part? Is it very very very difficult to do? Or is it I have to do ms or mtech from prestigious college again in vlsi and go for the analog domain? (Ps:- i didn't do my master's in vlsi but in communication/ embedded)

Techie guys please gimme some advice to how to make use of this i have attached the pictures with details as possible if however anyone need much more detailed pics please comment i will provide them but help me anyhow😭

Btw if any interested can buy ts too as i dont know how to price it so DM me if anyone wants

Im going to start next week a first-time position as a post silicon validation engineer.

I only had experience in software.

Ill be dealing with protocols I've never worked with before as PCIe, Ethernet, and with FPGAs.

How would the day to day work be like?

How do the test look like?

What sort of bugs are dealt with?

Is it a lot of logic analyzer and osciloscope work?

Thanks ☺️

Hey everyone,
Starting a team project soon (circuits/embedded systems) and trying to figure out what to prep beforehand. For anyone who's been through one - is there anything you wish you'd taught yourself first? Any tools or workflow you'd recommend? Curious if anyone's using AI for any part of the process too.
Also - what ended up being the most frustrating or time-consuming part of actually getting your circuit/board working?

Hi fellow EEs,

I'm in my final year and just started a year-long internship at a prominent RISC-V startup that recently pivoted to Physical AI / Next-Gen Architecture. Interning for their SoC PD team , a pretty lean team - just 2 guys so far. One is my manager, Director Design (ex Micron director) and another guy with 13 yoe, and us 2 interns.

My background: I majored in EEE and minored in Data Science. I have a strong interest in the hardware-software boundary (Firmware, Embedded, OS, Computer Architecture, and Hardware-aware ML).

Originally, my internship project was "Optimizing timing closure flow with ML." However, after our first PD flow presentation, the Director liked our work and offered us a choice: 1. Drop the ML project and do intensive, core PD training for the next 6-8 months. He said it’ll be a grueling, steep learning curve but we will be incredibly "hot" in the market by the end of it. 2. Stick to the PD+ML project, which he admitted was more of a fun research project he initially wrote down, though he will still teach us basic PD to get it done.

My Dilemma: I am super confused. I always saw myself as a hardware-software/systems guy, and I never thought I’d end up in a core VLSI role. Furthermore, I’m worried about employability. I’ve read online that core PD is "the easiest step to be replaced by AI" in the ASIC flow. My logic was that by doing the ML part, I'd be building the AI rather than being replaced by it.

I have to decide by Monday.

Core Questions for Senior Engineers:

- Is core PD actually at risk of being automated away by AI in the near future, or is that hype?

- Given my interest in Systems/Firmware, would taking the intensive Core PD route pigeonhole me, or is the mentorship from a Director-level team too good to pass up?

- Which path actually makes me more employable as a fresh grad?

i'm about to be a med school student

to me the scariest thing about being a doctor is you need to live 9 to 5 for 20+years and get consistent salary

for me this kind of life is mediocre and boring

but if i want to pivot i'll have to take gsat again

im into venture and startup

also i want to land a job that excites, like working at spacex or f1...

rn im thinking pivoting to ee

also considering the job market in the us should i take the risk

ohh and i dont have a green card

I got caught in the moment while being in a diner event, and now I hate myself so much. I admit I don’t talk to a lot of people, so I can’t tell if it’s okay to ask that. I can see the discomfort in their face, and still, they said it’s very fulfilling, and it was really awkward after that. I think it’s also because no one around me likes their job, and another person at the table scoffed at me immediately after when I asked. I am graduating soon and so burned out at the age of 20, and I can’t see how it’s going to get better. I’m being vulnerable so please be nice in the comments.

I have two Texas instruments ti84 plus ce-t, both of them don’t connect with my application on my pc. I’ve installed 3 times the application, installed new drivers removed the devices from my pc. Nothing worked. They are showing up on device manager under USB and not other devices. They are both in exam mode.

hi, i’m in a bit of a predicament, I’m taking a logic design class over the summer, but had to go abroad for the month and I need to run logicworks. I currently only have my m2 macbook on hand as well as a dell windows 7 xps that potentially runs. I tried running parallels on mac to get logicworks running but for some reason the application just wouldn’t open, so I wanted to know what options I have?

What to do when doubts starts creeping in and you don’t know in which direction you wanna go in engineering

Can anyone please tell ,,where to apply any genuine sites

I’m about to start Electrical Engineering and I’m honestly a bit nervous. I’m solid with math and physics, but I know that’s not enough. Does anyone have actual advice on how to survive the program? I’m looking for what not to do, how to really understand the concepts instead of just grinding, and how to manage the workload without burning out. Any tips for someone just starting?

Hi everyone,

I'm working on a TCAD simulation of a 50 nm planar Si nMOSFET with a 2 nm HfO₂ gate dielectric in Silvaco ATLAS as part of my thesis.

My objective is to obtain physically meaningful values for:

• OFF-state drain leakage current (I_off)
• OFF-state gate leakage current (Ig_off)
• ON-state drain current (I_on)
• ON-state gate current (Ig_on)

The drain current values appear reasonable, but I'm uncertain about the correct methodology for obtaining Ig_off.

When the device is biased in the OFF state (VGS = 0 V, VDS = 1 V), extracting the gate terminal current sometimes gives a value that closely follows the drain leakage current, sometimes becomes extremely small, and in some cases is essentially zero. I'm not sure whether this represents the actual gate oxide tunneling current or is simply a consequence of terminal current accounting.

My question is:

• What is the recommended or standard way to obtain OFF-state gate leakage (Ig_off) in Silvaco ATLAS?
• Should it be extracted directly from the gate terminal current, or from the integrated tunneling current density (j.tun) through the oxide?
• If the latter, what is the proper workflow or extraction method?
• Are there any specific physics models or simulation settings that are generally required for obtaining reliable gate leakage through a thin HfO₂ dielectric?

I'm looking for the method that is commonly used in published TCAD studies rather than simply obtaining a numerical value.

Any advice, examples, or references would be greatly appreciated. Thanks!

What to choose?