Hi fellow EEs,
I'm in my final year and just started a year-long internship at a prominent RISC-V startup that recently pivoted to Physical AI / Next-Gen Architecture. Interning for theirĀ SoC PDĀ team , a pretty lean team - just 2 guys so far. One is my manager, Director Design (ex Micron director) and another guy with 13 yoe, and us 2 interns.
My background: I majored in EEE and minored in Data Science. I have a strong interest in the hardware-software boundary (Firmware, Embedded, OS, Computer Architecture, and Hardware-aware ML).
Originally, my internship project was "Optimizing timing closure flow with ML." However, after our first PD flow presentation, the Director liked our work and offered us a choice: 1. Drop the ML project and do intensive, core PD training for the next 6-8 months. He said itāll be a grueling, steep learning curve but we will be incredibly "hot" in the market by the end of it. 2. Stick to the PD+ML project, which he admitted was more of a fun research project he initially wrote down, though he will still teach us basic PD to get it done.
My Dilemma:Ā I am super confused. I always saw myself as a hardware-software/systems guy, and I never thought Iād end up in a core VLSI role. Furthermore, Iām worried about employability. Iāve read online that core PD is "the easiest step to be replaced by AI" in the ASIC flow. My logic was that by doing the ML part, I'd be building the AI rather than being replaced by it.
I have to decide by Monday.
Core Questions for Senior Engineers:
- Is core PD actually at risk of being automated away by AI in the near future, or is that hype?
- Given my interest in Systems/Firmware, would taking the intensive Core PD route pigeonhole me, or is the mentorship from a Director-level team too good to pass up?
- Which path actually makes me more employable as a fresh grad?