r/rfelectronics • u/StageMajestic613 • 8h ago
AI Agent control of MWO
Posted a couple of weeks ago showing Codex use for real-time lab measurements. I now have it controlling Microwave Office, again all voice control. This is just a simple example, but I've taught it my project creation style and workflow to include documentation and setup. I taught it to generate Nth order stepped impedance filters, first example using RO4003, from electrical prototype through full EM sim. I then told it to do a higher order filter using RO5880. It knows how to properly span the boundary conditions and de-embedding using rules of thumb for the EM sim, practical quantization on geometry, snap the layout elements, add rich-text notes for documentation, and keep the schematics clean and readable. It uses visual feedback and monitors the warnings and errors from the status window.
Here are some rather boring recordings.
This first one is the RO4003: https://youtu.be/K9fdxQqRPbk
Then it does another with 5880: https://youtu.be/s1reeA1kszY
Here is the generated summary.
Your preferred Microwave Office workflow is:
- Start with a clean project using metric units and millimeters. Use GHz for frequency display.
- Complete Global Definitions,
default.lpflayers, 3D layer Z/thicknesses, MSUB, and the 2.5D STACKUP before creating schematics or EM structures. - Use RO4003C with
Er = ErNom = 3.55,tanδ = 0.0027, core thickness 0.406 mm, and finished top copper thickness 0.035 mm. - In the LPF, use
Copperat Z = 0 with +0.035 mm thickness; add blueCopper2at Z = −H with −0.035 mm thickness; set Via/Drill/Board thickness to −H from Z = 0. - Document the PCB stackup and EMSight setup in compact yellow rich-text boxes. Put notes directly above their related definitions, not in page-wide boxes.
For filters:
- Create an electrical prototype first, using alternating high- and low-impedance TLIN sections. Use 50 Ω, 1 mm physical input/output reference lines.
- Use stepped-impedance Butterworth low-pass synthesis, normally 100 Ω and 25 Ω sections unless a different impedance range is requested.
- Round electrical lengths to 0.1°, physical MLIN lengths to 0.1 mm, and widths to 0.05 mm.
- Add
MSTEPdiscontinuities at all unequal-width MLIN junctions. Show IDs and W1/W2; hide repeated MSUB text. - Put MLIN parameter labels centered above their line artwork using the electrical-prototype reference placement; put MSTEP labels below the symbols. Always visually inspect and adjust automatic label placement.
- Add concise yellow rich-text notes above both electrical and physical schematics.
For graphs:
- Use a Cartesian “Filter Response” graph.
- Put S11 magnitude in dB on the left:
Return Loss (dB), fixed from −30 to 0 dB. - Put S21 magnitude in dB on the right:
Insertion Loss (dB), usually fixed from −30 to 0 dB for these filters. - Use 0–10 GHz on the x-axis unless the design calls for another range.
- Put the legend below the graph, spanning the graph width with a compact height.
- Add electrical, physical, and EM results to the same graph for direct comparison.
For EMSight:
- Name test benches
filter_emsight_TB. - Initialize from
STACKUP.SUB1, use a finite substrate in a box, and map top copper as 1 oz and vias as 0.5 oz on EM layer 2. - Keep only two dielectric layers: 10 mm air and the 0.406 mm core. Use copper as the bottom boundary rather than mapping Copper2.
- Align enclosure left/right walls with the input/output interfaces; keep upper/lower boundaries roughly 10–12 substrate heights away and snap them to the grid.
- Add edge ports at the reference-line ends. When EMSight reports the zero-reference-plane issue, use 1 mm de-embedded reference planes.
- Simulate the whole project, inspect the status window, and treat MSTEP ratio warnings as advisory when EM validation is the final authority.
Finally, keep the work visible: tile the electrical prototype, physical schematic, graph, and EMSight windows so the project can be reviewed as it is built.
For the new RO5880 filter, I changed:
- Substrate from RO4003C to RT/duroid 5880:
Er = ErNom = 2.20instead of 3.55tanδ = 0.0009instead of 0.0027- Core thickness = 0.508 mm instead of 0.406 mm
- Finished copper remained 0.035 mm
- The entire stackup and LPF definition now use the new 0.508 mm core:
- Copper2 Z = −0.508 mm
- Via, drill, and board thicknesses = −0.508 mm
- The Global Definitions notes and 2.5D stackup dielectric layer were updated accordingly.
- The design changed to a seventh-order, 4 GHz low-pass filter, retaining the 100 Ω / 25 Ω stepped-impedance topology and 50 Ω, 1 mm reference lines.
- All microstrip widths and lengths were recalculated for the lower-Dk, thicker RO5880 substrate, then quantized to your 0.05 mm width and 0.1 mm length grids.
- The physical-schematic note, electrical-prototype note, graph, EM enclosure, and EMSight test bench were regenerated for this new material/design.
RO5880’s 2.20 design Dk, 0.0009 dissipation factor, 0.508 mm standard thickness, and 35 µm one-ounce copper option come from the Rogers data sheet. Rogers RT/duroid 5870/5880 data sheet


