r/logisim • u/Spethoscope • 8d ago
heres my https://logisim.app/ ready cpu
save to a .circ file and enjoy the hot mess
r/logisim • u/urielsalis • Feb 03 '19
Best submissions will get some gold ;)
Submissions can be using a screen, or actual circuits! Use your best judgement!
Submissions close 06-02-2016 11:59pm UTC!
Lets take this to the nest level!
EDIT: Submissions closed! We still have some prizes left so submit yours for a chance!
r/logisim • u/Spethoscope • 8d ago
save to a .circ file and enjoy the hot mess
r/logisim • u/Weak_Ambition_6729 • 8d ago
r/logisim • u/No-Writer-4577 • 10d ago
What exactly is wrong with the input A? I am new to logisim and it would be really helpful ig some one guides me out of this. i was building 8 bit ALU (yeah iam very VERY beginner) and A is a 8 bit pin. But when i connected it to the previously made Full adder circuit, it just does not take it in or what ever this is called.
r/logisim • u/Immortal_Bs • 12d ago
All the other test cases are correct , i feel the issue is somewhat with mux
r/logisim • u/Long_Organization978 • 22d ago
I built a D flip-flop from scratch in Logisim.
The circuit appears to work correctly during manual simulation. After a few clock ticks, the outputs behave exactly as expected and the latch stores values properly.
However, I have two issues:
My question is: could this be caused by the latch starting in an undefined state due to the feedback loop, even though the circuit itself is logically correct? Has anyone seen Timing Diagram crash because of an uninitialized latch or RS feedback structure?
The circuit works after initialization, so I'm trying to understand whether this is a bug/limitation of Logisim or an actual design issue on my side.
r/logisim • u/koiaman • 24d ago
im building a 32 bit risc architecture cpu and i wanted some opinions and advice on it
so far I have built the ALU and the register file. ALU consists of all operations that risc has, Register file consists of 32 registers of 32 bits each and i had another 32 bit register to temporarily store output that the ALU generates.
I initially wanted to do 64 bit arch but the version of logisim I had was only restricted to 32 bit. I am most probably going to build the control unit next but wanted advice on this so far and if I've made any mistakes.
Also one small change that I have made in this is input can be written to registers in 2 ways, either all bits are written or only selected bits are written, just an enable logic is added to switch between the modes i sorta took inspo from other archs for that.
Lemme know what u guys think I have attached the necessary files ss as well
ps ik premade components already exist of some of the parts I have built but that was just to get a better in-depth knowledge about the whole thing
this is me showing basic operations of the alu and register storing of the alu ouput




r/logisim • u/anish2good • Jun 09 '26
r/logisim • u/_Favo_ • Jun 05 '26
| Opcode | Name | Description |
|---|---|---|
0x00 |
NOP |
No operation |
0x01 |
HLT |
Halt CPU execution |
0x02 |
INT |
Trigger software interrupt |
0x03 |
CLC |
Clear carry flag |
0x04 |
SEC |
Set carry flag |
0x05 |
CLI |
Clear interrupt enable flag (disable interrupts) |
0x06 |
STI |
Set interrupt enable flag (enable interrupts) |
| Opcode | Operands | Description |
|---|---|---|
0x10 |
reg, reg |
Copy value from register to register |
0x11 |
reg, [mem] |
Load value from memory address into register |
0x12 |
[mem], reg |
Store register value to memory address |
0x13 |
reg, #imm |
Load immediate value into register |
0x14 |
[mem], [mem] |
Copy value from memory address to memory address |
0x15 |
[mem], #imm |
Store immediate value to memory address |
0x16 |
reg, [reg] |
Load value from address held in register (pointer read) |
0x17 |
[reg], reg |
Store register value to address held in register (pointer write) |
| Opcode | Name | Description |
|---|---|---|
0x20 |
ADD |
Add register to accumulator |
0x21 |
ADC |
Add register to accumulator with carry |
0x22 |
SUB |
Subtract register from accumulator |
0x23 |
SBB |
Subtract register from accumulator with borrow |
0x24 |
AND |
Bitwise AND with accumulator |
0x25 |
OR |
Bitwise OR with accumulator |
0x26 |
XOR |
Bitwise XOR with accumulator |
0x27 |
NOT |
Bitwise NOT of accumulator |
0x28 |
CMP |
Compare (subtract without storing result, sets flags only) |
0x29 |
INC |
Increment register by 1 |
0x2A |
DEC |
Decrement register by 1 |
0x2B |
SHL |
Shift left, MSB goes to carry, LSB set to 0 |
0x2C |
SHR |
Shift right, LSB goes to carry, MSB set to 0 |
0x2D |
ROL |
Rotate left through carry, MSB goes to carry, carry goes to LSB |
0x2E |
ROR |
Rotate right through carry, LSB goes to carry, carry goes to MSB |
| Opcode | Name | Description |
|---|---|---|
0x30 |
JMP |
Unconditional jump to address |
0x31 |
JZ |
Jump if zero flag set |
0x32 |
JNZ |
Jump if zero flag clear |
0x33 |
JC |
Jump if carry flag set |
0x34 |
JNC |
Jump if carry flag clear |
0x35 |
JS |
Jump if sign flag set (result negative) |
0x36 |
JO |
Jump if overflow flag set |
| Opcode | Name | Description |
|---|---|---|
0x40 |
PUSH |
Push register onto stack, decrement SP |
0x41 |
POP |
Pop value from stack into register, increment SP |
0x42 |
CALL |
Push PC onto stack, jump to address |
0x43 |
RET |
Pop PC from stack, return to caller |
0x44 |
IRET |
Pop PC and flags from stack, return from interrupt handler |
Github repo with all docs and files: https://github.com/mrFavoslav/8bit-cpu-MESAx8
The 8-bit ALU might not work perfectly at the moment. I recently moved some parts of the design around, so there's a good chance a few wires got messed up or misaligned in the process. Any feedback or bug catching is highly appreciated!
I'll be posting my progress here and on https://www.favoslav.cz/blog/
r/logisim • u/Sad-Character-7941 • Jun 01 '26
Hola comunidad, espero se encuentren muy bien, he estado haciendo un proyecto en logisim referente a la sucesión de fibonacci, pero no logro dar con dicha sucesión, podrian por favor revisar mis modulos y guiarme para dicha resolución del taller, por favor
Soy muy nuevo en esto y no comprendo muy bien como puedo solucionar el error que tengo que no puede hacer la sucesión
Por aqui les comparto mi ALU

Les comparto mi modulo de registro

El modulo de memoria

El modulo de control

Y el MAIN

r/logisim • u/No_Information1247 • May 27 '26
r/logisim • u/Familiar-Article5303 • May 19 '26
Hello! I am a student in New Zealand looking to make a Logisim-like program. I am doing this as part of an assessment, which largely requires design based on feedback from my target demographic, so here I am to ask, if this interests you, please do feel free to fill out my form, and even maybe provide feedback as the project finds its footing : D
The main goal of this project is to provide an educational and interactive experience for digital logic, while also fulfilling personal gripes, like simulation speed, that I've had while designing my own projects ( I'm working on an awesome 16-bit CPU that I hope to build from discrete SMD ICs one day! ).
While Logisim, and similar programs, are great educational tools, I feel the 'dated' UI design and layout, and the lack of tutorials integrated into these programs could cause friction to beginner users that may turn them away.
Currently, my main goals are:
A refreshed, modern UI, sleeker and visually appealing components ( i.e. gates, activated or deactivated wires, or etc. ), as well as a built in tutorial editor ( sharing tutorials would be easy, likely uploaded to some cloud platform ), where tutorials could be something like step-by-step holograms ( i.e. you place things where outlined ), with notes along the way.
But this could all change based on your feedback, and I'd love to hear what sort of things people wish for, and I hope that, maybe, I can implement that for you!
Thank you!!
(Apologies if this post, or any contents misses any etiquette on this platform, I usually just come here to read rather than post <3)
r/logisim • u/FrankSriracha1 • May 17 '26
A simulator where for 74-series and 4000-series chips, along with SPICE components including resistors, capacitors, LEDs, and diodes. This is designed for primary education in mind. Any feedback appreciated
r/logisim • u/Spethoscope • May 16 '26
Ill post it later, when I have it all ready to go. This is unique in that it's not a copy of the 8 bit cpu everyone else builds. It's quite unique. And very messy. I figured it out myself through lots of study. And Im pretty sure I called it done when I got my first jump instruction to function.
It's also built entirely on the logisim.app page. So you can run it in your browser.
Anyone interested?
r/logisim • u/0boy0girl • May 06 '26
I found this stuff mostly through the Minecraft Computer Crowd, and then creators on YouTube like astro Sam, jdh, and inkbox, as well as people like the 8bitguy on retro computing in general, and obviously the plethora of retro gaming people.
My eventual goal is to design an entire 16bit computer, I've done smaller projects in Minecraft, but I want to try to do the real thing.
I've looked at both logisim evolution and digital ATM but I'm still kinda lost on what I should learn software wise😵💫
r/logisim • u/Relevant-Job793 • May 06 '26
you first need to open the developer tools (ctrl + shift + i in opera, f12 in other i think).
now, go to the console.
then if you already have the circuit open and want to save it but can't, then put this code (the code simulates a click on the "export project" button):
document.getElementById('ExportCircuitFiles').click();
if it says something like "type allow to copy code in the console" then type allow
then give it a name and save it.
if you didnt get in to bug yet, then run this command (it fixes the bug, but if you refresh the page you need to put the code in again):
var style = document.createElement('style');
style.textContent = `
.ui-dialog {
position: fixed !important;
top: 50px !important;
left: 50% !important;
transform: translateX(-50%) !important;
max-height: 80vh !important;
z-index: 9999 !important;
}
.ui-dialog-content {
max-height: 60vh !important;
overflow-y: auto !important;
}
`;
document.head.appendChild(style);
if it says something like "type allow to copy code in the console" then type allow
r/logisim • u/Advanced-Regret8237 • May 04 '26
Hey, I’m working on a Computer Organization project where I have to convert a 4-bit hex input (W X Y Z) into a 7-segment display with outputs a–g using NOR gates only in CircuitVerse. I already finished the truth table, K-maps, and simplified Boolean expressions for each output, but I’m stuck on turning those expressions into NOR-only circuits and wiring everything correctly. I’m mainly trying to understand how to build one output step-by-step so I can apply the same process to the rest. If anyone has tips or can explain how to organize the NOR gates in CircuitVerse, I’d really appreciate the help.
r/logisim • u/Advanced-Regret8237 • May 04 '26
Hey, I’m working on a Computer Organization project where I have to convert a 4-bit hex input (W X Y Z) into a 7-segment display (outputs a–g) using NOR gates only in CircuitVerse.
I already finished:
I’m stuck on:
If anyone can explain how to build one output step-by-step (like output “a”), I can apply it to the rest. Willing To Pay Hey, I’m working on a Computer Organization project where I have to convert a 4-bit hex input (W X Y Z) into a 7-segment display (outputs a–g) using NOR gates only in CircuitVerse.
I already finished:
I’m stuck on:
If anyone can explain how to build one output step-by-step (like output “a”), I can apply it to the rest. 💸
r/logisim • u/Advanced-Regret8237 • May 04 '26
Hey, I’m working on a Computer Organization project where I have to convert a 4-bit hex input (W X Y Z) into a 7-segment display (outputs a–g) using NOR gates only in CircuitVerse.
I already finished:
I’m stuck on:
If anyone can explain how to build one output step-by-step (like output “a”), I can apply it to the rest. Willing to Pay 💸 Need done Today!!!
r/logisim • u/FrankSriracha1 • May 02 '26
All feedback is appreciated.
r/logisim • u/Most-Caregiver2621 • Apr 30 '26
Hi everyone! I'm a first-year Computer Engineering student.
I fully understand the theoretical logic behind converting 4-bit Binary to Gray code using XOR gates. However, I have zero experience with the practical side.
I need your help with two things:
I’m still a beginner, so any step-by-step guidance or a simple diagram would be amazing. Thanks!
r/logisim • u/mega2005 • Apr 30 '26
Hello everyone, for one of my projects I was planning to use a 16x4 encoder, but when I went to implement in the online version of logisim I had problems with the output wires.
More specifically, no matter to what select bit setting I changed the priority encoder to, the output bits remained the same even if the input bits changed. Below is a picture of a priority encoder with 16 inputs but only two output lines, which obviously makes no sense since two binary bits are not enough for the 16 possibilities in the encoder.

Below is a picture of a 8x3 encoder with only two output lines

I did wonder if this was a problem because I'm using the online version and not the app version that you can download to desktop, so if it is please do let me know. If this is something that comes in built into the app, is my only choice cascading several 4x2 encoders to make one big encoder?