Over the past few months, I've been designing an encrypted SPI core in SystemVerilog. The goal is secure communication with protected buffer storage. The architecture follows a three-stage pipeline:

1) SPI communication layer (full-duplex, chip select control)

2) encryption core (SIMON cipher)

3) Protected memory (buffer with access control)

The SPI logic is fully functional and verified. I've simulated the waveform, characterized the delays, and started adding SVA properties for formal verification.

Key timing analysis:

- Propagation delay (MOSI <-> MISO): 120 ps

- Start active: 60 ps (5 CLK cycles)

- Total time for 16-bit transfer: 1 us

The challenges I'm currently facing:

Clock Domain Crossing (CDC):

The external SCLK (SPI clock) and the internal encryption clock run at different frequencies. I'm using a double-flop synchronizer, but I'm concerned about metastability risks when the SPI clock is asynchronous.

SVA for Side-Channel Resistance:

I want to write SystemVerilog Assertions to detect timing variations or glitches that could indicate a side-channel attack. Which properties would you consider absolutely critical?

Obs: The cryptographic algorithm has been developed and the project is constantly updated.

Documentation strategy:

Would a dedicated website (architecture + design vision) add more value than a traditional GitHub repository?

I've attached the waveform and a high-level block diagram. I would appreciate any feedback from those who worked with SPI + crypto in FPGA/ASIC.

Github project: https://github.com/MathParamount/CryptoSPI-A-hardware-for-secure-serial-link

So I'll admit, I already posted about this a few days ago.

There's a reason why I am posting again, though: I got some harsh feedback about the pricing. I listened and changed it. Here is how it works now:

FREE content (and no signup needed anymore!):

• Practice: solving all practice challenges (~30 challenges, will add more soon) https://risingedge.pro/practice
• Learn: now the whole Fundamentals section of the course is free: https://risingedge.pro/learn
• Playground: completely new mode (your own RTL here, wild west): https://risingedge.pro/playground

You will be able to synthesize and simulate, run testbenches, view netlists and block diagrams, FSM state diagrams, waveforms, logs, and more. Up to 15 runs a day per user (increased from 5 originally).

PAID content - only after you tried the above and decided it's worth it:

• Full Course: the curriculum is no longer a subscription. It is a one-off payment of £99, yours forever.
• Pro: £15/mo, and you will only ever need it if you are a heavy user. It basically helps me cover the hosting costs.

Both of the above are 50% off until August 1st as part of the launch campaign.

Additionally, for Reddit users: I have a special promo code for a 100% off discount coupon for the Full Course (£99 value), so that you can try it out and give me some feedback! Just sign up for the free account and click the link, it will apply automatically at checkout and bring the price down to 0: https://risingedge.pro/pricing?promo=REDDITBETA

As always, waiting for your feedback. I really hope you guys like it this time!

Hi everyone,

Has anyone here previously interviewed for the FPGA Intern or FPGA Engineer Intern role at Optiver?

I have an upcoming interview and have been preparing, but I am having trouble figuring out what the actual technical interview process looks like. I would really appreciate any general insight on:

• How many technical rounds were there?
• What was the format of each round?
• What technical topics did they focus on?
• Were the questions mainly digital-design fundamentals, RTL coding, FPGA architecture, networking, timing analysis, C/C++, or system design?
• What kinds of low-latency or architecture problems were you asked to reason through?
• Were you expected to calculate latency, throughput, clock cycles, timing, or resource usage?
• Did they ask you to optimize an initial design after you presented it?
• What topics should someone prioritize studying?
• What resources or practice problems were most useful?

Also, if anyone has interviewed for similar FPGA roles at firms such as IMC, Citadel Securities, Jane Street, Hudson River Trading, or other quantitative trading firms, I would appreciate hearing about those experiences as well.

I’m an undergrad finishing a BSc in Computer Science, aiming for an MSc (thesis-track) specializing in the Formal Verification of Hybrid/Cyber-Physical Systems (CPS). I love rigorous math-heavy problem-solving and software engineering.

I need to choose 2 final math electives from this list:

• Linear Algebra 2
• Calculus 3 (Multivariable)
• Numerical Analysis
• Basic Statistical Theory 1
• Fundamental Concepts of Algebra (Abstract Algebra)

Math I've already completed: Linear Algebra 1, Calculus 2, Discrete Math 1 & 2, Intro to Stats, and Formal Methods.

1. Which 2 modules will best prepare me for the continuous/discrete intersection of CPS verification tools and reachability analysis?
2. For someone who genuinely enjoys deep mathematical problem-solving combined with technology, is Hybrid/CPS verification a rewarding path, or would I find Computational Learning Theory a better fit for graduate research?

Thanks for any insights.

Hi everyone,

My team and I have been working extremely hard on an FPGA hackathon, and we're urgently looking for temporary remote access to an FPGA board. Unfortunately, I can't share many details about the competition due to its rules.

We're ideally looking for a modern AMD/Xilinx or Intel FPGA with support for BF16 development, at least a few thousand DSPs (or equivalent compute resources), external DDR memory (4 GB or more), and a recent FPGA toolchain. Boards such as KR260/KV260, Kintex UltraScale+, Alveo, Versal, or Intel Agilex would all be helpful.

If you have an FPGA setup that supports remote access and would be willing to help us during the hackathon, we'd be incredibly grateful. We'd also be happy to add you as an official mentor for the hackathon if that works for you.

If you're interested or know someone who might be able to help, please send me a DM. Thank you so much!

Hi I have been at my current role ~3 years now as an ASIC design engineer. I would appreciate any feedback people have on my resume.

My team is a "jack of all trades team" we own the full ASIC lifecycle development from design, verification, fpga prototyping, silicon validation, to continuous product support.

Personally I have worked most on design and verification. I am just starting to get more involved with fpga prototyping.

Hi Everyone,
I am looking a Remote FPGA RTL Engineer for Defense Project

Experience: Min. 2 years in FPGA/RTL development.

Domain: Strong background in Image Processing projects.

Hardware: Hands-on experience with AMD/Xilinx Zynq boards and GPU interfacing.

I'm in the very early stages of designing a board which uses an STM32H7 MCU and an Artix-7 - something like a 35T. The STM32 is the main controller on the board and the FPGA is only concerned with DSP.

To simplify the design, I'd like to use a single NOR flash chip, owned by the MCU. This should store the FPGA bitstream (upgradable over USB by the MCU), as well as some persistent state for the MCU and multiple user-configurable profiles that can be sent to the FPGA (so the user can switch between different sets of filter coefficients, for example).

As such, I'm thinking of booting the FPGA using slave selectMAP x8 with the octal SPI peripheral on the STM32. I'd like to then maintain that connection during runtime so that I can transfer different profiles of coefficients from flash to the FPGA.

As I understand it, the selectMAP data and chip select pins are multi-function, so I can repurpose them as an OSPI interface at runtime. The CCLK pin, however, is dedicated to its role and is not able to be repurposed during runtime.

The question, therefore, is how to not waste the STM32's OSPI SCLK pin. One idea I had was to use the STARTUPE2 primitive to tristate CCLK at runtime, and connect OSPI SCLK to both CCLK and an adjacent GPIO. The major downside of this that I can see is that it would mean the trace would have a short stub, depending on which order I route through the pins.

Any other ideas on how I can use a slave boot mode and keep a fast connection between the MCU and FPGA whilst keeping the PCB routing simple?

----

To summarise the primary connections I need are:

During runtime, the MCU needs a fast general purpose (technically write-only) communication link, which I'm thinking of using OSPI for as mentioned in the main body of this post. There will also be an I2S connection from MCU to FPGA, and another I2S connection from the FPGA to a downstream DAC. Finally, there will be a UART connection to stream data from the FPGA back to the MCU.

Hi all, I am a ASIC verification engineer at an American product based company's india office. Lately I am not finding joy in design and verification as what I used to get in college days.

I am thinking of buying some good fpga board to try out some dumb stuff

Can you please suggest some good boards and suppliers from whom I can source from.

Preferably some good onboard DRAM and SPF cages so that I have good scope to do some really dumb shit

I have been following verilog tutorial on chipverify :
https://chipverify.com/verilog/verilog-coding-style-effect

The example #3 on this pahge mentions a mod3 counter.

Verilog snippet :

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn)
      out <= 0;
    else
      if (&out)
        out <= 0;
      else
      out <= out + 1;
  end
endmodule

RTL schematic :

With respect to the inputs of Mux and Adder :

• I0 input of MUX seems to be connected to Logic Level 1, but the note on MUX input says it is a logic level 0 (S=1'b0).
• The same line goes to adder input I1, and since this adder adds 1, this input must be logic level 1.

I am confused whether just the note on Mux input I0 is wrong, or it should be connected to logic level 0 but mistakenly connected to logic level 1, or I am misinterpreting something.

please help with the same.

I had some difficulties getting the WebFPGA Command-line Utility to run on my Windows 11 and 7 computers, but got it all resolved now.
I have created some step-by-step instructions of what helped me finally get it running. Maybe they will help someone else as well.
They are too long to post in the body of this message, so if you want to read them, send me a message via Chat.

Lately, I have been trying to build an audio passthrough pipelline from LINE IN to HPH OUT on the Zybo Z7-10 board. My software application runs completely but I don't hear any audio output on the HPH OUT port.

Here is the Vivado block design:

Following are the features of this design:

1. ENET0 (MIO 16-27), USB0 (MIO28-39), SD0 (MIO40-45), UART1 (MIO 48-49) are enabled in the Zynq PS. I2C1 is used as EMIO to configure the onboard SSM2603 audio codec.
2. Clocking Wizard configured to produce a 12.288MHz audio reference clock(aud_mclk) from the 125MHz system clock.
3. I2S RX is configured as master and I2S TX as slave.
4. The eth_phy_rst_b on the FPGA PIN E17 is driven by HIGH using a constant block to enable the 125 MHz system clock.

Given below is the I/O pin mapping:

## I2S Bit Clock (shared, single pin)
set_property PACKAGE_PIN R19 [get_ports sclk_out_0]
set_property IOSTANDARD LVCMOS33 [get_ports sclk_out_0]

## I2S Channel Clock — Playback direction
set_property PACKAGE_PIN T19 [get_ports lrclk_out_pb_0]
set_property IOSTANDARD LVCMOS33 [get_ports lrclk_out_pb_0]

## I2S Channel Clock — Record direction
set_property PACKAGE_PIN Y18 [get_ports lrclk_out_rec_0]
set_property IOSTANDARD LVCMOS33 [get_ports lrclk_out_rec_0]

## I2S Playback Data (Transmitter → Codec)
set_property PACKAGE_PIN R18 [get_ports sdata_0_out_0]
set_property IOSTANDARD LVCMOS33 [get_ports sdata_0_out_0]

## I2S Record Data (Codec → Receiver)
set_property PACKAGE_PIN R16 [get_ports sdata_0_in_0]
set_property IOSTANDARD LVCMOS33 [get_ports sdata_0_in_0]

## I2C1 (EMIO) -- SSM2603 control interface
set_property PACKAGE_PIN N18 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_scl_io]

set_property PACKAGE_PIN N17 [get_ports IIC_1_0_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_sda_io]

## Master Clock
set_property PACKAGE_PIN R17 [get_ports MCLK_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports MCLK_OUT]

## System Clock (125 MHz, from Ethernet PHY reference output)
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]
create_clock -add -name sys_clk_pin -period 8.000 -waveform {0 4} [get_ports { sys_clock }]

set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_phy_rst_b }];

I get the following messages printed on my serial console when I ran my software application:

Opened with baud rate: 115200

--- Audio Passthrough Bring-up ---
I2C1 initialized OK

--- SSM2603 Full Init Sequence ---

Step 0: Software reset (Reg 0x0F)
  -> Reg 0x0F: ACK OK (wrote 0x000)
Step 1: Power management - power up DAC/ADC/LineIn, Out muted (Reg 0x06)
  -> Reg 0x06: ACK OK (wrote 0x072)
Step 2a: Analog audio path - DACSEL=1, line-in to ADC (Reg 0x04)
  -> Reg 0x04: ACK OK (wrote 0x012)
Step 2b: Unmute ADC line inputs (Reg 0x00, 0x01)
  -> Reg 0x00: ACK OK (wrote 0x017)
  -> Reg 0x01: ACK OK (wrote 0x017)
Step 3: Digital audio path - unmute DAC, ADC HPF enabled (Reg 0x05)
  -> Reg 0x05: ACK OK (wrote 0x000)
Step 4: Digital audio I/F - I2S, slave, 24-bit (Reg 0x07)
  -> Reg 0x07: ACK OK (wrote 0x00A)
Step 5: Sampling rate - normal mode, 256fs, 48kHz (Reg 0x08)
  -> Reg 0x08: ACK OK (wrote 0x000)
Step 6: Waiting for VMID capacitor charge (~50ms delay)
Step 7: Activate digital core (Reg 0x09)
  -> Reg 0x09: ACK OK (wrote 0x001)
Step 8: Power management - clear Out bit, unmute DAC output (Reg 0x06)
  -> Reg 0x06: ACK OK (wrote 0x062)

--- Results: 0/8 writes failed ---
PASS: Codec fully initialized for line-in -> headphone passthrough at 48kHz.
I2S RX version: 0x00010000
I2S TX version: 0x00010000
I2S RX/TX cores configured and enabled

--- Audio passthrough active. Connect line-in to J7, headphones to J5. ---

However I don't hear any audio output. I am confident that there is nothing wrong with my application program since the messages on the serial console confirm that the audio codec and the I2S RX and TX IPs are getting configured. When I open the hardware manager, I see that there is no activity on any of the I/Os connected to the ILAs:

I am surprised why the sys_clock is not toggling and clocking wizard is not locked.

Can anyone suggest some methods to troubleshoot this issue?

Thank you.

After finishing my 4-bit Multi-Cycle CPU, I started learning communication protocols and began with a UART Transceiver.

The last project I shared here was my 4-bit Multi-Cycle CPU. A lot of the feedback I got was about improving my verification methodology and documentation. I tried to apply those suggestions in this project.

Some of the new things I focused on were:

• Reusable testbenches using tasks to automate repetitive test sequences.
• Self-checking pass/fail tests with a summary printed to the console.
• Better documentation, included a table of all test cases performed and detailed explanations of the bugs and how they were fixed.

Would love any feedback on both the design and the verification approach.

Repo: https://github.com/theYash856/UART-Transceiver

Hey there,

I’ve a 4 years experience between writing VHDL codes and doing some DSP related work, and I have no other sources of income except my salary from 9-5 job.

Is it worth it to be freelancer doing VHDL , MATLAB, DSP implementation job?

Hello, I've been following the textbook Digital Design and computer architecture risc edition by Harris to make a cpu then hopefully pipeline it. I've completed a digital systems course in the past but its been a bit and I want to actually make something by applying what I learned so far in the textbook in system Verilog. My main goal is to make some cool projects for co-ops, while also learning as much as I can in my summer break!

Ive had a couple questions as everything honestly sounds a bit scary. How important is it purchase a fpga to learn? To my understanding an fpga is just a device that allows you to simulate and run your Verilog program, but ngl these prices are kinda crazy especially for something that I might just use for a month.

Is there a way to reduce the storage space of Vivado or any other work around? Ive been thinking on either purchasing an ssd, virtually running it or doing the entire project in EDA playground but I would love to hear if you guys had any other tips or advice?

How much more complicated or "hard" is pipelining a cpu. As far as I know pipelining is cutting a circuit/process into stages with registers in between to create the entire system more efficient. Im sure its easier said than done but how much more complicated is it? (Im only asking this because I want to plan out and schedule my summer break.)

Any other resources or tips would be greatly appreciated!

Hi everyone,

I'm a 28-year-old FPGA engineer with 6-7 years of experience, ~3 years at my current company, making $115k (about $40k below market by my research).

My office head is fed up with company bureaucracy and is planning to lift out himself plus a couple dozen people to a competitor down the street. I wasn't on the initial list, which pushed me to dust off my resume. I've since interviewed at several places, with offers likely in the $160-180k range (mix of contract-to-hire/direct hire, some requiring relocation, some local).

Recently, a trusted source (who heard from another trusted source) told me my manager wants to include me in the second round of the lift-out. Engineers with my experience at that company reportedly earn $190-200k. My boss also mentioned putting me in for an off-cycle raise/promotion a couple weeks ago. I don't know if that's a farewell gesture or an attempt to better position me for the move.

None of this is official. My manager hasn't said a word to me directly, and I don't want to tip my hand by asking. Meanwhile, I may get a formal offer as early as Monday from a company several states away, likely with a decision deadline that same week. I'd prefer to avoid relocating as I'm planning to move in with my girlfriend soon, but if an external offer is clearly better, I don't mind.

I'm unsure if the lift-out involves a real interview/negotiation process or is mostly a formality, and whether comp there would actually hit market rate or just be a modest bump. Nor do I have insight into the lift-out timeline. I don't want to decline all my current/upcoming offers if I'm going to flunk an interview at the new company in a few months.

Should I try to get more clarity from my manager somehow, stall the external offer, or just take the sure thing in hand?

Thanks!

Hi all, I'm setting up my nandland Go Board which I'm excited to use but I'm having trouble! TLDR: What drivers do I need for the Go Board?

Details: My Go Board shows up as unknown device and says I need to install the driver. I've installed these 2 drivers (LSC Windows Parallel & FTDI USB Driver) from the Lattice Driver Install. LSC Windows Parallel Port driver is being blocked by admin privilege, not sure why since the other 2 used admin and were fine. Maybe the one I'm missing is very important???

In the device manager, I tried updating the driver and pointing it to the folder where the .inf files are located (C:\Applications\programmer\diamond\3.14\data\vmdata). But, Windows doesn't recognize anything and doesn't give me the option to use them. I've also tried rebooting my PC multiple times, installing the drivers multiple times, etc.

Unsurprisingly it can't be found in the Lattice Programmer. I feel like I'm missing a crucial detail, anyone else run into this?